Compilers and Programming LanguagesReading Group
|Where||E1 3, Room 401|
If you want to participate, please register with Klaas Boesche until 2011-10-23.
- Informal meeting
- In the week before each meeting, a recent research paper is chosen by a participant and distributed to everyone.
- Be prepared to ask questions about the paper with regard to what you did not understand, future work, technical details, etc.
- The paper is then presented by that participant and discussed in the group.
- For the short presentation and summary you can use the black board. Slides are not necessary.
- Every student participating obtains 2 credit points (free section) iff he/she misses at most two meetings and presents at least one paper
- 2011-10-24 - Klaas Boesche: Tal Lev-Ami et al. - Backward Analysis for Inferring Quantified Preconditions
- 2011-11-02 - Christoph Mallon: Finding and Understanding Bugs in C Compilers
- 2011-11-09 - Roland Leißa: A Domain-Specific Approach To Heterogeneous Parallelism
- 2011-11-16 - Prashant Yadawa: Practical Memory Checking with Dr. Memory
- 2011-11-23 - Michael Jacobs: Improving the Static Analysis of Loops by Dynamic Partitioning Techniques
- 2011-11-30 - Klaas Boesche: Logical Abstract Domains and Interpretations
List of Papers (Suggestions)
On the list below are papers that someone in the group would find interesting to discuss and are suggestions for the participants. If you have additional suggestions or want to present and discuss something else do not hesitate to write a mail or mention it at the meeting.
- Inferable Object-Oriented Typed Assembly Language
- Finding and Understanding Bugs in C Compilers
- MAO - an Extensible Micro-Architectural Optimizer
- Practical Memory Checking with Dr. Memory
- Intel's Array Building Blocks: A Retargetable, Dynamic Compiler and Embedded Language
- Flow-Sensitive Pointer Analysis for Millions of Lines of Code
- Runtime Automatic Speculative Parallelization
- JPure: A Modular Purity System for Java
- Using Disjoint Reachability for Parallelization
- Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures