CDL Group Seminar Seminar
In this seminar, members and guests of our group as well as students preparing a bachelor or master thesis in our group meet weekly to present their work. Furthermore, all participants discuss recent research papers.
- Bachelor/Master Seminar
- If you want to do a thesis in our group, you will have to attend this seminar. For UdS students: This seminar counts as the Bachelor/Master Seminar.
- Reading Group
- Other students are cordially invited to discuss recent research papers. These students obtain 3 credit points.
General Information
When | Thursdays at 14:00 (sine tempore) |
Where | Room 401, E1 3 |
The first seminar meeting will be on 18 October 2018.
Modus Operandi - Reading Group
- On the first meeting each participant chooses a recent research paper.
- Later on, this student will present the paper while all other participants must also read the paper to ask questions with regard to what they did not understand, future work, technical details, etc.
- For the short presentation and summary students can use the black board. Slides are not necessary.
- On each session we will either discuss a research paper or attend a presentation by a current Bachelor/Master student who presents his/her work.
- Every student participating obtains 3 credit points (free section) iff he/she misses at most two meetings and presents at least one paper
Papers
You can find the paper list in our Wiki. In order to access the Wiki you need to register in our GitLab and email Roland Leißa your GitLab username.
Modus Operandi - Bachelor/Master Seminar
You need to:
- Find a topic and an advisor and read related work (literature etc.) which is not part of the master seminar itself.
- Discuss related work and your approach with your advisor.
- Attend the seminar at least 10 times. Your attendance can start at any time and need not be completed within a single semester.
- Write and submit a proposal (see regulations below).
- Give a talk in which you explain your plans for the thesis (this means presenting the contents of your proposal) [graded].
- Start working on your thesis.
- Submit the thesis in the term after you got the seminar schein. If you fail to do so, you will need to attend another master seminar (probably at another chair) before you are allowed to start another thesis.
- Give a final talk in the seminar.
The first time you show up at the master seminar, make sure to give us your email address. It will be added to the mailing list and you will receive email notifications before each upcoming session.
After getting the Schein, students need to register their thesis at the Prüfungsamt.
Proposal Regulations
Although the thesis proposal is not part of the master seminar itself, we require a proposal to contain:
- A problem description.
- Discuss related work.
- State a hypothesis which explains how to solve the problem.
- Name potential risks, assumptions and restrictions of your approach (as well as possible solutions).
- Validation and evaluation of your approach.
- Time schedule
- Length 5 to 10 pages
- Must-have features: Things your thesis must cover to be successful
- May-have features: Things your thesis can cover to improve its value
- Out-of-scope features: Things your thesis will not cover (although one may think so)
A presentation of such a thesis proposal must meet the following requirements:
- length about 25 minutes
- plus 5-10 minutes for questions
Schedule
Date | Speaker | Topic | Comments |
---|---|---|---|
2018-10-18 14:00 s.t. | Kallistos Weis | Portable Instruction-Throughput Estimation for Port-Mapping Synthesis | Bachelor proposal |
2018-11-08 14:00 s.t. | - | Producing wrong data without doing anything obviously wrong! | Paper discussion |
2018-11-22 14:00 s.t. | Roland Leißa | A Compiler-Compiler for DSL Embedding | Paper discussion |
2018-11-29 14:00 s.t. | Wiam Rachid | Auto-Vectorizing C++-Code | Master talk |
2018-12-06 14:00 s.t. | Roland Leißa | ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS | Paper discussion |
2019-01-10 14:00 s.t. | Matthis Kruse | An FPGA-Implementation of Sequence Alignment in AnyDSL | Bachelor proposal |
2019-01-17 14:00 s.t. | Fabian Ritter | Reverse-Engineering Port-Mappings of Out-of-Order Processors | - |
2019-01-24 14:00 s.t. | Jannic Warken | Adaptive Execution of Compiled Queries | Paper discussion |
2019-01-31 14:00 s.t. | Jannis Roth | Register Allocation in LLVM | Bachelor talk |
2019-02-14 14:00 s.t. | Dominik Luche | Web Browser Based C and MIPS Interpreters for Educational Purposes | Bachelor proposal |
2019-02-21 14:00 s.t. | tba | tba | - |
2019-02-28 14:00 s.t. | tba | tba | - |
2019-03-07 14:00 s.t. | Matthias Kurtenacker | tba | Master proposal |
In cases of questions, do not hesitate to ask Roland Leißa.