Compilers and Programming Languages

Organization

If you want to participate, please register with Ralf Karrenberg until 2011-04-12.

Modus Operandi

• Informal meeting
• Every meeting, a recent research paper is presented and discussed
• Use the black board. No slides necessary
• Every student participating obtains 2 credit points (free section) iff he/she misses at most two meetings and presents at least one paper

Papers

• 2011-05-02: Sebastian Hack: EigenCFA: Accelerating flow analysis with GPUs
• 2011-05-09: Klaas Boesche: Precise Interprocedural Dataflow Analysis with Applications to Constant Propagation
• 2011-05-16: Sigurd Schneider: An axiomatic basis for computer programming [ additional material: Separation Logic (Sections 1-5)]
• 2011-05-23: No session
• 2011-05-30: Liviu Teris: Taint Dependency Sequences: A Characterization of Insecure Execution Paths Based on Input-Sensitive Cause Sequences
• 2011-06-06: No session
• 2011-06-13: No session
• 2011-06-20: Steven Schäfer: Optimizing for Space and Time Usage with Speculative Partial Redundancy Elimination
• 2011-06-27: Hazem Torfah: Dependent Types In Lambda Cube
• 2011-07-04: Johannes Doerfert: Loop Parallelization in the Polytope Model [ additional material: Polly: Polyhedral Optimizations for LLVM ]
• 2011-07-11 (tentative): Svilen Dimitrov: Finding and Understanding Bugs in C Compilers
• 2011-07-18: Nasimi Eldarov: An experiment about static and dynamic type systems: doubts about the positive impact of static type systems on development time

List of Papers

• Inferable Object-Oriented Typed Assembly Language
• Finding and Understanding Bugs in C Compilers
• MAO - an Extensible Micro-Architectural Optimizer
• Practical Memory Checking with Dr. Memory
• Intel's Array Building Blocks: A Retargetable, Dynamic Compiler and Embedded Language
• Flow-Sensitive Pointer Analysis for Millions of Lines of Code
• Runtime Automatic Speculative Parallelization
• JPure: A Modular Purity System for Java
• Using Disjoint Reachability for Parallelization
• Data Layout Transformation for Stencil Computations on Short-Vector SIMD Architectures